Process for producing semiconductor device

ABSTRACT

A process for producing a semiconductor device for forming a highly reliable wiring structure is provided that solves the problem occurring on using a xerogel or a fluorine resin in an inter level dielectric between the wirings to decrease a wiring capacitance, and the problem occurring on misalignment. A process for producing a semiconductor device comprising an inter level dielectric containing a xerogel film or a fluorine resin film comprises a step of forming, on the inter level dielectric comprising a lower layer of the inter level dielectric formed with an organic film and an upper layer of the inter level dielectric formed with a xerogel film or a fluorine resin film, a first mask to be an etching mask for forming a via contact hole by etching the inter level dielectric, and a step of forming, on the first mask, a second mask, which comprises a different material from the first mask, to be an etching mask for forming a wiring groove by etching the inter level dielectric.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a process for producing a semiconductordevice, and more particularly, it relates to a process for producing asemiconductor device having a multi-layer wiring structure used fordevice process beyond the design rule of 0.25 μm.

2. Description of the Related Art

With the scale down of a semiconductor device, scale down of wiring andreduction of a wiring interval become necessary. Simultaneously, withthe demand of low consuming electric power and high-speed operation, aninter level dielectric having a low dielectric constant and wiringhaving a low resistance become necessary. Particularly, in a logicdevice, because increase of the resistance and increase of the wiringcapacitance due to the fine wiring bring about deterioration inoperation speed, fine multi-layer wiring using a film having a lowdielectric constant as an inter level dielectric becomes necessary.

In order to apply the dual damascene method to the inter leveldielectric having a low dielectric constant, in which a conductivematerial is filled in a via hole and a wiring groove formed in the interlevel dielectric, followed by flattening, it is necessary to employ atechnique in which the via hole and the wiring groove can besimultaneously formed in the inter level dielectric having a lowdielectric constant.

An organic polymer is receiving attention as the material for the interlevel dielectric having a low dielectric constant. An organic polymerhas a dielectric constant of about 2.7, which is lower than theconventional inter level dielectric using silicon oxide (SiO₂) having adielectric constant of about 4.0 and silicon oxide fluoride (SiOF)having a dielectric constant of about 3.5. Therefore, a greatimprovement in performance is expected in a semiconductor device usingan organic polymer in an inter level dielectric. However, as the organicpolymer is an expensive material, taking the balance between increase incost and improvement in performance of the semiconductor device intoconsideration, it has been studied a structure, in which only the interlevel dielectric having groove wiring formed therein is formed with theorganic polymer, and the inter level dielectric having a via hole formedtherein is formed with silicon oxide or silicon oxide fluoride, whichhas been conventionally used. An example of such a structure will bedescribed below with reference to FIGS. 1A to 1F.

As shown in FIG. 1A, a passivation film 111 comprising a material, intowhich a wiring material is not diffused, is formed with a siliconnitride film on a substrate 110, in which transistors and wiring havebeen formed, and then a first inter level dielectric 112, in which a viahole is to be formed, is formed with a silicon oxide film having athickness of 500 nm. A resist mask (not shown in the figure) for forminga via hole is formed on the first inter level dielectric 112, and a viahole 113 is formed in the first inter level dielectric 112 by etchingusing the resist mask as an etching mask. The resist mask is thenremoved.

As shown in FIG. 1B, a second inter level dielectric 114, by which thevia hole 113 is filled, is formed with an organic polymer having athickness of 500 nm on the first inter level dielectric 112.

As shown in FIG. 1C, a mask layer 115 to be an etching mask for forminga wiring groove is formed with a silicon oxide film having a thicknessof 100 nm on the second inter level dielectric 114. A resist mask 116for forming a wiring groove pattern is formed on the mask layer 115. Anopening 117 for forming the wiring groove pattern is formed in theresist mask 116.

As shown in FIG. 1D, the wiring groove pattern 118 is formed in the masklayer 115 by etching using the resist mask 116 as an etching mask.

As shown in FIG. 1E, the second inter level dielectric 114 is etched byusing the resist mask 116 (see FIG. 1D) and the mask layer 115 as anetching mask to form a wiring groove 119, and the second inter leveldielectric 114 filled in the via hole 113 is selectively removed tore-open the via hole 113 in the first inter level dielectric 112. Uponetching in this case, since the second inter level dielectric 114comprising the organic polymer is etched, the resist mask 116 issimultaneously etched and removed. Therefore, a step of removing theresist mask 116 is not necessary.

Thereafter, as shown in FIG. 1F, the passivation film 111 exposed at thebottom of the via hole 113 is etched by using the first and second interlevel dielectrics 112 and 114 as a mask. As a result, the wiring groove119 and the via hole 113 having a dual damascene structure are formed.

The scale down of the wiring width and reduction of the interval bringabout not only the aspect ratio of the wiring itself, but also theaspect ratio of the space among the wiring, and as a result, and thusdifficulties are caused in the techniques for forming narrow and longwiring and the technique for filling a gap among fine wiring with aninter level dielectric. Thus, the process becomes complicated, andsimultaneously the number of steps contained in the process isincreased.

In a damascene process, in which after a via hole and a wiring grooveare simultaneously filled with an aluminum series metal or a copperseries metal by reflow sputtering, an excess metal on the inter leveldielectric, in which the via hole and the wiring groove are formed, isremoved by chemical mechanical polishing (hereinafter referred to asCMP), it is not necessary to form metallic wiring having a high aspectratio by etching or to fill the gap among the wiring with an inter leveldielectric, and thus the number of steps of the process can be greatlyreduced. This process contributes to the reduction of the total cost ina greater extent when the aspect ratio of the wiring becomes larger, orthe total number of the wiring becomes larger.

An inter layer dielectric having a low dielectric constant is applied toa device of a 0.18 μm or lower design role rule since it reduces thecapacitance among the wiring. A film having a specific inductivecapacity of 2.5 or less has a film property that is greatly differentfrom a silicon oxide film used in the conventional device, and thus aprocess technique that can be applied to the film having a lowdielectric constant is demanded.

Many of the films having a low dielectric constant of 3.0 or lower areorganic films containing carbon, and they are employed instead of theconventional inter level dielectric. Oxygen is necessarily used onopening a via hole in the organic film used as the inter leveldielectric. However since a resist comprising an organic film is used inthe patterning technique used in the conventional process for producinga semiconductor device, there is a problem in that the film having a lowdielectric constant is damaged in the step of removing the resist.Because the composition of the film having a low dielectric constant issimilar to the composition of the resist, there is a possibility thatthe film having a low dielectric constant is removed in the step ofremoving the resist.

In recent years, an application of xerogel to a semiconductor device isreceiving attention as a material expected to have a specific inductivecapacity of 2.0 or less. The xerogel is a well-known material, forexample, as silica gel used as a desiccating agent. The application ofxerogel to a semiconductor device is difficult at present due to ademand of various kinds of reliability. That is, xerogel contains from50 to 90% of pores by volume and thus has a problem in mechanicalstrength.

In the process described with reference to FIGS. 1A to 1F, the secondinter level dielectric is filled in the via hole in the step shown inFIG. 1B. Therefore, in the step shown in FIG. 1E, because the secondinter level dielectric in the via hole is etched until it is completelyremoved, over etching is often applied to the bottom of the wiringgroove and the mask layer. As a result, the shoulder parts of the bottomof the wiring groove and the mask layer are cut by a sputteringphenomenon, and a wiring groove and a via hole having a good shape aredifficult to be obtained. In the case where the interval of the wiringgrooves is narrow, the wiring grooves adjacent to each other areconnected due to the cutting of the shoulder parts of the mask layer, soas to cause a defect such as a short circuit.

In the process technique shown in FIGS. 1A to 1F, when the wiring grooveis formed beyond. the via hole due to misalignment, the contact area ofthe via hole becomes small to cause problems, such as increase of thecontact resistance, defective filling of the metal in the via hole, anddeterioration of resistance to electro-migration. The misalignment willbe described in detail below with reference to FIGS. 2A to 2F.

As similar to the case shown in FIGS. 1A and 1B, after forming apassivation film 111 on a substrate 110, a first inter level dielectric112 is formed, and then a via hole 113 is formed in the first interlevel dielectric 112, as shown in FIG. 2A. As shown in FIG. 2B, a secondinter level dielectric 114 filling the via hole 113 is formed on thefirst inter level dielectric 112.

As shown in FIG. 2C, after forming a mask layer 115 on the second interlevel dielectric 114, a resist mask 116 for forming a wiring groovepattern is formed on the mask layer 115. An opening 117 for forming thewiring groove pattern is formed in the resist mask 116. At this time, itis assumed that the opening 117 is formed deviating from the via hole113 due to misalignment.

As shown in FIG. 2D, a wiring groove pattern 118 is formed in the masklayer 115 by etching using the resist mask 116 as an etching mask.

As shown in FIG. 2E, the second inter level dielectric 114 is etched byusing the resist mask 116 (see FIG. 2D) and the mask layer 115 as anetching mask to form a wiring groove 119, and the second inter leveldielectric 114 filled in the via hole 113 is selectively removed tore-open the via hole 113 in the first inter level dielectric 112. Atthis time, because the wiring groove 119 is formed deviating from thevia hole 113 due to the misalignment, the second inter level dielectric114 remains in a part of the via hole 113 to stuff up a part of the viahole 113, and thus the opening area is decreased.

As shown in FIG. 2F, the passivation film 111 exposed at the bottom ofthe via hole 113 is etched by using the first and second inter leveldielectrics 112 and 114 as a mask. When the wiring groove 119 and thevia hole 113 having a dual damascene structure are formed as describedin the foregoing, because a part of the via hole 113 is stuffed up bythe second inter level dielectric 114, the contact area becomes small tocause increase in contact resistance.

SUMMARY OF THE INVENTION

An object of the invention is to provide a process for producing asemiconductor device for solving the problems described in theforegoing.

The invention relates to a process for producing a semiconductor devicecomprising an inter level dielectric comprising a xerogel film or anorganic film, the process comprising a step of forming, on an interlevel dielectric, a first mask to be an etching mask for etching theinter level dielectric; and a step of forming, on the first mask, asecond mask comprising a different material from the first mask to be anetching mask for etching the inter level dielectric.

Because the process for producing a semiconductor device of theinvention comprises the step of forming, on an inter level dielectric, afirst mask to be an etching mask for etching the inter level dielectric;and the step of forming, on the first mask, a second mask comprising adifferent material from the first mask to be an etching mask for etchingthe inter level dielectric, after the inter level dielectric is etchedby using the first mask as an etching mask, the inter level dielectriccan be etched by using the second mask as an etching mask to a patterndifferent from the first mask.

In the process for producing a semiconductor device, a lower layer ofthe inter level dielectric formed between wiring layers may be formedwith an organic film, and an upper layer of the inter level dielectricformed between wiring of the same wiring layer may be formed with axerogel film or an organic film.

In this embodiment of the production process, since the upper layer ofthe inter level dielectric formed between wiring of the same wiringlayer is formed with a xerogel film or an organic film, such as afluorine resin film, the dielectric constant between wiring of the samewiring layer, which becomes the maximum wiring capacitance, can be aboutfrom 1.8 to 2.4, and thus the wiring capacitance can be reduced.

Specifically, in a semiconductor device having the minimum interval ofwiring, in particular, one of a design rule of 0.18 μm or less, axerogel film or an organic film, such as a fluorine resin film, isapplied to the part where the wiring interval is 0.3 μm or less. Whilethe wiring capacitance is generally remarkably increased at the partwhere the wiring interval is 0.3 μm or less, an effect of decreasing thewiring capacitance can be obtained by using the xerogel film or theorganic film, such as a fluorine resin film.

On the other hand, there is no large influence relating to the increasein capacitance at the part where the wiring interval is larger than 0.3μm (for example, one between wiring layers vertically stacked).Therefore, it is sufficient to use an organic film having a specificinductive capacity of 3 or less at the part where the wiring intervalexceeds 0.3 μm. A fluorine resin film may also be used as the organicfilm. As described in the foregoing, scale down of the wiring intervalcan be realized in the invention. Furthermore, by using a xerogel filmor an organic film, such as a fluorine resin film, only between thewirings, and by using an organic film having a low dielectric constantof 3 or less for the other parts, the remarkable deterioration of themechanical strength of the whole inter level dielectrics can besuppressed. In the case where the upper layer of the inter leveldielectric is formed with an organic film, the lower layer of the interlevel dielectric can be formed with an organic film, and the samefunction described in the foregoing can also be obtained in this case.

In the process for producing a semiconductor device of the invention, apattern for forming the wiring groove may be formed in the second mask,and a pattern for forming the via hole is formed in the first mask insuch a manner that the pattern for forming the via hole at leastoverlaps the pattern for forming the wiring groove. That is, the processfor producing a semiconductor device may comprise, a step of forming, onthe inter level dielectric, a first film for forming the first mask; astep of forming, on the first film, a second film for forming the secondmask; a step of forming the second mask by forming a pattern or formingthe wiring groove in the second film; and a step of forming the firstmask by forming a pattern for forming the via hole in the first film issuch a manner that the pattern for forming the via hole at leastoverlaps the pattern for forming the wiring groove.

In this embodiment of the production process, the resist process usedfor forming the first and second masks can be conducted under thecondition in that the inter level dielectric is not exposed. That is, inthe resist process for forming the second mask, the first film is formedas an underlayer, and in the resist process for forming the first mask,the first film itself covers the inter level dielectric. Thus, therestoration treatment of the resist process can be conducted.

Even when misalignment occurs on forming the pattern of the first maskfor forming the via hole, the pattern for forming the via hole can alsobe formed in the second mask, and there is no possibility that theopening area of the via hole is reduced as described with reference toFIGS. 2A to 2F.

Furthermore, because the first mask and the second mask are formed witha material having light transmissibility, the so-called mask alignment,where the position of the mask is aligned to the underlayer uponexposure, can be conducted by an alignment method using light or analignment method using an image processing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F are cross sectional views showing a process diagram of aproduction process according to the conventional technique.

FIGS. 2A to 2F are cross sectional views showing a process diagram of aproduction process according to the conventional technique wheremisalignment occurs.

FIGS. 3A to 3F, 4G and 4H are cross sectional views showing a processdiagram of a first embodiment of the process for producing asemiconductor device according to the invention.

FIGS. 5A to 5C are cross sectional views showing a process diagram of asecond embodiment of the process for producing a semiconductor deviceaccording to the invention.

FIGS. 6A to 6F are cross sectional views showing a process diagram of athird embodiment of the process for producing a semiconductor deviceaccording to the invention.

FIGS. 7A to 7I are cross sectional views showing a process diagram of afourth embodiment of the process for producing a semiconductor deviceaccording to the invention.

FIGS. 8A to 8F are cross sectional views and plan views showing aprocess diagram of a fourth embodiment of the process for producing asemiconductor device according to the invention where misalignmentoccurs.

DESCRIPTION OF PREFERRED EMBODIMENTS

A first embodiment of the process for producing a semiconductor deviceaccording to the invention will be described below with reference to theprocess diagram shown in FIGS. 3A to 3F, 4G and 4H.

As shown in FIG. 3A, an underlying substrate 11 comprises, for example,a substrate 51 having thereon transistors (not shown in the figure), andan inter metal dielectric 52 covering thereon, in which wiring 53 isformed. A first film having a low dielectric constant 13 to be a lowerlayer of an inter level dielectric 12 is formed on the underlyingsubstrate 11 to a thickness of, for example, from 300 to 800 nm. Thefirst film having a low dielectric constant 13 becomes an inter leveldielectric (ILD) between wiring layers, and can be formed with anorganic film having a specific inductive capacity of about 2.5. In thisembodiment, an organic polymer totally called as polyaryl ether isemployed. Specific examples of the polyaryl ether include flare (atradename, produced by Aliedsignal Inc.), SILK (a trade name, producedby Dow Chemical Corp.) and VELOX (a trade name, produced by SchumacherCorp.). Alternatively, a BCB (bis-benzocyclobutene) film, a polyimidefilm and an amorphous carbon film may be used.

The formation of the organic polymer can be conducted, for example, by aprecursor is coated as a film on the underlying substrate 11 by spincoating, and then cured at a temperature of from 300 to 450° C. In thecase where the surface of the underlying substrate 11 is hydrophobic,and the adhesion to the organic film is poor, or in the case wherediffusion of copper is prevented, while not shown in the figure, asilicon oxide film, a silicon oxide nitride film, a silicon carbide filmor a titanium nitride silicate film is formed.

The silicon oxide film can be formed, for example, by the followingmanner. A commercially available SOG (spin on glass, for example, an SOGmainly comprising silanol, and an SOG mainly comprising a polymercontaining silanol) is coated to a thickness of from 30 to 100 nm by aspin coating method. The coated film is baked at a temperature of from150 to 200° C. for about 1 minute, and then cured at a temperature offrom 350 to 450° C. for about from 30 to 60 minutes.

The silicon oxide film may be formed by a plasma CVD (chemical vapordeposition) method using a commercially available plasma CVD apparatus.In the case where the wiring 53 is copper wiring, it is not preferred toform the silicon oxide film by a normal plasma CVD method because thecopper wiring is oxidized. However, the copper wiring can be preventedfrom oxidation as possible by using dinitrogen monoxide (N₂O) gas as theoxidizing agent, using a silane series gas (for example, monosilane(SiH₄), disilane (Si₂H₆) or trisilane (Si₃H₈)) as the silicon source,setting the substrate temperature to 300 to 400° C., setting the plasmapower to 350 W, and the pressure of the film forming environment toabout 1 kPa.

In the case of the silicon nitride oxide film, a commercially availableinorganic SOG containing an amino group may be, for example, by formedinto a film by a spin coating method. It is preferred that the filmformation is conducted by the plasma CVD method. Examples of the gasused in the plasma CVD method include a silane series gas (monosilane(SiH₄), disilane (Si₂H₆) or trisilane (Si₃H₈)) as the silicon source,ammonia and hydrazine as the nitriding agent, and dinitrogen monoxide(N₂O) as the oxidizing agent. As the carrier gas, an inert gas, such asnitrogen, helium and argon, is employed. The film formation isconducted, for example, under such conditions that the substratetemperature is from 300 to 400° C., the plasma power is 350 W, and thepressure of the film forming environment is about 1 kPa.

In the case of the silicon nitride film, it can be formed by spincoating of a commercially available inorganic SOG containing an aminogroup as similar to the case of the silicon nitride oxide film. It ispreferred that the film formation is conducted by the plasma CVD method.Examples of the gas used in the plasma CVD method include a silaneseries gas (monosilane (SiH₄)), disilane (Si₂H₆) or trisilane (Si₃H₈))as the silicon source, ammonia and hydrazine as the nitriding agent, anddinitrogen monoxide (N₂O) as the oxidizing agent. As the carrier gas, aninert gas, such as nitrogen, helium and argon, is employed. The filmformation is conducted, for example, under such conditions that thesubstrate temperature is from 300 to 400° C., the plasma power is 350 W,and the pressure of the film forming environment is about 1 kPa.

The silicon carbide film can be formed, for example, by using a parallelflat palate type plasma CVD apparatus. Examples of the gas used in theplasma CVD method include methyl silane as the silicon source. The filmformation is conducted, for example, under such conditions that thesubstrate temperature is from 300 to 400° C., the plasma power is from150 to 350 W, and the pressure of the film forming environment is aboutfrom 100 Pa to 1 kPa.

A second film having a low dielectric constant 14 to be an upper layerof the inter level dielectric 12 is formed to a thickness, for example,of 400 nm on the first film having a low dielectric constant 13. Thesecond film having a low dielectric constant 14 is formed with afluorine resin. Examples of the film include a fluorocarbon film, suchas a cyclic fluorine resin, polytetrafluoroethylene (PTFE), amorphousPTFE (for example, Teflon AF, a trade name, produced by Du Pont Corp.),fluorinated aryl ether and fluorinated polyimide. Alternatively, axerogel (for example, porous silica) may be employed.

The film of the fluorine resin can be formed by the manner, in which aprecursor of the fluorine resin is coated on the first film having a lowdielectric constant 13 by a spin coating apparatus, and then cured at atemperature of from 300 to 450° C. The materials, such as fluorinatedamorphous carbon, can be formed by a plasma CVD method using acetylene(C₂H₂) and a fluorocarbon gas (for example, octafluorobutane (C₄F₈)) asthe process gas. In this case, the film thus formed is cured at atemperature of from 300 to 450° C. The amorphous PTFE is not limited toTeflon AF and may be any substance having the structure represented bythe following formula (1):

wherein m and n each represent a positive integer.

As the second film having a low dielectric constant 14, acyclopolymerized fluorinated polymer series resin (for example, Cytop, atrade name) may be used. The cyclopolymerized fluorinated polymer seriesresin is not limited to Cytop and may be any substance having thestructure represented by the following formula (2):

wherein x, y and z each represent a positive integer.

As the second film having a low dielectric constant 14, a fluorinatedpolyaryl ether series resin (for example, FLARE, a trade name) may beused. The fluorinated polyaryl ether series resin is not limited toFLARE and may be any substance having the structure represented by thefollowing formula (3);

wherein R represents an alkyl group.

In the case where a xerogel is used as the second film having a lowdielectric constant 14, Nanoporous Silica developed by Nanoglass LLC isformed into a film by using a spin coating apparatus developed byNanoglass LLC. Nanoporous Silica is a kind of porous silica, and thexerogel that can be used in the invention is not limited to NanoporousSilica. That is, any type of xerogels that can be formed by thefollowing method can be used. A silanol resin having an alkyl grouphaving a relatively high molecular weight, such as an aromatic group, iscoated on a substrate and gelled, and the film is then subjected to ahydrophobic treatment by using a silane coupling agent or ahydrogenating treatment.

According to the manner described in the foregoing, the inter leveldielectric 12 comprising the first film having a low dielectric constant13 and the second film having a low dielectric constant 14 is formed onthe underlying substrate

As shown in FIG. 3B, a first film 15 for forming a first mask as aninorganic mask is formed with a silicon oxide film having a thickness offrom 50 to 300 nm on the inter level dielectric 12, i.e., on the secondfilm having a low dielectric constant 14. A second film 16 for forming asecond mask is formed with a silicon nitride film having a thickness offrom 50 to 150 nm. In the film forming method of these films, anordinary CVD apparatus is used under the same conditions as described inthe foregoing.

Before forming the silicon oxide film, it is preferred that a filmhaving a larger silicon content than the silicon nitride film, theamorphous silicon nitride film, the silicon oxide film or thestoichiometric amount is formed, depending on necessity, particularly inthe case where the oxidation of the second film having a low dielectricconstant 15 causes a problem. That is, a CVD film is formed under areductive atmosphere. The film thickness is preferably as thin aspossible, and is generally about 10 nm. As described herein, the firstfilm 15 is formed with a silicon oxide film that is excellent in lighttransmissibility in a wavelength range (for example, from 200 to 1,000nm) used for alignment, and the second film 16 is also formed with asilicon nitride film having light transmissibility in a wavelength range(for example, from 200 to 1,000 nm) used for alignment.

As the inorganic mask, a metallic film or a metallic compound film, suchas titanium, titanium nitride, tantalum and tantalum nitride, can beused, as well as the silicon nitride film. The film thickness thereof ispreferably from 50 to 150 nm. The film formation thereof can beconducted by sputtering, which is generally employed in film formationof a metallic film and a metallic compound film.

As shown in FIG. 3C, a resist film 17 is formed on the second film 16 byan ordinary resist coating technique (for example, a spin coatingmethod). Thereafter, the resist film 17 is patterned by a lithographytechnique to form openings 18 for forming wiring grooves.

Subsequently, only the second film 16 is etched by using the resist film17 as an etching mask to form openings 19 for forming wiring grooves, soas to form a second mask 21 to be an etching mask for forming wiringgrooves in the inter level dielectric 12. In this step, only the secondfilm 16 is selectively etched by using an ordinary magnetron typeetching apparatus. As the etching conditions where the second film 16comprises a silicon nitride film, for example, trifluoromethane (CHF₃)(5 cm³/min), oxygen (O₂) (5 cm³/min) and argon (Ar) (20 cm³/min) areused as the etching gas, and an RF plasma is set at 600 W. In the casewhere the second film 16 comprises a metallic compound film, a chlorineseries etching gas, such as boron chloride (BCl) and chlorine (Cl₂), isused as the etching gas. Thereafter, the resist film 17 is removed byashing. FIG. 3C shows the state before removing the resist film 17.

As shown in FIG. 3D, a resist film 22 is formed on the second film 16and the first film 15 by an ordinary resist coating technique (forexample, a spin coating method). Thereafter, the resist film 22 ispatterned by a lithography technique to form openings 23 for forming viaholes at positions within the openings 19 for forming the wiring groovesfrom the plan view of the second film 16.

Subsequently, only the first film 15 is etched by using the resist film22 as an etching mask to form openings 24 for forming via holes in theinter level dielectric 12, so as to form a first mask 25 to be a etchingmask for forming the via holes in the inter level dielectric 12.

The second film having a low dielectric constant 14 of the inter leveldielectric 12 is etched by using an ordinary etching apparatus using theresist film 22 as an etching mask. As the etching conditions, forexample, hexafluoroethane (C₂F₆) (14 cm³/min), carbon monoxide (180cm³/min) and argon (240 cm³/min) are used as an etching gas, and an RFplasma is set at 1.5 kw. Because the first film having a low dielectricconstant 13 comprising an organic film is present as an underlayer ofthe second film having a low dielectric constant 14, the etching isstopped at the upper surface of the first film having a low dielectricconstant 13.

As shown in FIG. 3E, the first film having a low dielectric constant 13is etched by using an ordinary etching apparatus using the first mask 25as an etching mask, to form via holes 26 in the inter level dielectric12. As an etching gas in the etching, nitrogen is used, and ammonia anda hydrogen gas are also used depending on necessity. At the time wherethe first film having a low dielectric constant 13 comprising an organicfilm is etched, the resist film 22 (see FIG. 3D) is also etched andcompletely removed. Therefore, there is no necessity to conduct resistashing in this stage.

As shown in FIG. 3F, by using the second mask 21 comprising a siliconnitride film (or a metallic compound film), the first mask 25 is etched,and then the second film having a low dielectric constant 14 is etched,so as to form wiring grooves 27 in the second film having a lowdielectric constant 14. The etching conditions of this step are the sameas those for etching the second film having a low dielectric constant 14described in the foregoing.

As shown in FIG. 4G, wiring is formed by a damascene method. A barriermetal layer 31 comprising tantalum nitride is formed on the inner wallsof the wiring grooves 27 and the via holes 26 by sputtering or by a CVDmethod. At this time, the barrier metal layer 31 is also formed on thesecond mask 21. A wiring material (metal), such as copper, isaccumulated by sputtering, a CVD method or an electrolytic platingmethod. In the case where the metal 32 is accumulated by an electrolyticplating method, a seed layer (not shown in the figure) comprising thesame metal as the metal 32 to be accumulated is formed in advance.

Thereafter, an excess metal 32 and the barrier metal layer 31 on thesecond mask 21 are removed by polishing using CMP, and, as shown in FIG.4H, wiring 33 comprising the metal 32 is formed on the wiring grooves 27via the barrier metal layer 31, so as to form plugs 34 comprising themetal 32 in the via holes 26 via the barrier metal layer 31. In thisstep, the second mask 21 functions as a polishing stopper, but in somecases, the second mask 21 may be completely removed depending on thethickness of the second mask 21. In this CMP, for example, an aluminaslurry is employed.

While not shown in the figure, the process comprising from the step offorming the inter level dielectric 12 to the step of forming the wiring33 and the plugs 34 may be repeated to form a multi-layer wiring. Theinter metal dielectric 52 among the wiring 53 may be formed with axerogel film or a fluorine resin film by the similar process as theforegoing.

In the descriptions in the foregoing, while an example is described, inwhich the inter level dielectric 12 is formed on the underlyingsubstrate 11 having semiconductor elements formed therein, theproduction process can be applied to the case where the inter leveldielectric 12, the via holes 26, the wiring grooves 27, the wiring 33and the plugs 34 having the constitution described above are formed on asubstrate having no semiconductor element.

The process for producing a semiconductor device described in theforegoing comprises a step of forming, on the inter level dielectric 12,the first mask 25 to be an etching mask for etching the inter leveldielectric 12, and a step of forming, on the first mask 25, the secondmask 21 to bean etching mask for etching the inter level dielectric 12,the second mask 21 comprising a material different from the first mask25. Therefore, the inter level dielectric 12 is etched by using thefirst mask 25 as an etching mask to form the via holes 26, and then theupper layer of the inter level dielectric 12, i.e., the second filmhaving a low dielectric constant 14, is etched by using the second mask21 as an etching mask to a pattern for forming wiring grooves differentfrom the first mask 25, to form the wiring grooves 27.

Furthermore, because the upper layer of the inter metal dielectricbetween the wirings in the same wiring layer, i.e., the second filmhaving a low dielectric constant 14, is formed with a xerogel film or afluorine resin film, the dielectric constant between the wirings in thesame wiring layer where the wiring capacity becomes maximum is aboutfrom 1.8 to 2.4, and thus the wiring capacitance is reduced.Specifically, in a semiconductor device having the minimum interval ofwiring, in particular, one of a design rule of 0.18 μm or less, axerogel film or a fluorine resin film is applied to the part where thewiring interval is 0.3 μm or less. While the wiring capacitance isgenerally remarkably increased at the part where the wiring interval is0.3 μm or less, an effect of decreasing the wiring capacitance can beobtained by using the xerogel film or the fluorine resin film.

On the other hand, there is no large influence relating to the increasein capacitance at the part where the wiring interval is larger than 0.3μm (for example, one between the wirings 53 and the wiring 33)Therefore, it is sufficient to use an organic film having a specificinductive capacity of 3 or less at the part where the wiring intervalexcess 0.3 μm. As described in the foregoing, scale down of the wiringinterval can be realized in the invention. Furthermore, by using axerogel film or a fluorine resin film only between the wirings, and byusing an organic film having a low dielectric constant for the otherparts, the remarkable deterioration of the mechanical strength of thewhole inter level dielectrics can be suppressed.

Furthermore, the resist process (a step of patterning the resist film)for forming the first and second masks 25 and 21 can be conducted underthe condition where the inter level dielectric 12 is not exposed. Thatis, in the resist process for forming the second mask 21, the first film15 is formed as an underlayer, and in the resist process for forming thefirst mask 25, the first film 15 itself covers the inter leveldielectric 12. Thus, without exposing the inter level dielectric 12comprising an organic film, the resist films 17 and 22 formed by theresist process can be removed, and a restoration treatment of the resistwhere the resist films 17 and 22 are again formed and patterned can beconducted. Furthermore, because the resist film 22 to be an etching maskfor forming the first mask can be removed simultaneously to the etchingof the first film having a low dielectric constant 13, the operation ofremoving the resist film 22 by ashing is not necessary. Therefore, theprocess can be simplified.

In the resist process where the openings 24 to be a pattern for formingthe via holes are formed in the first mask 25, i.e., in the process forforming the openings 23 in the resist film 22, even when misalignmentoccurs to form the openings 23 formed in the resist film 22 deviatingfrom the openings 19 to be a pattern for forming the wiring grooves,because openings (not shown in the figure) to be a pattern for formingthe via holes can be formed in the second mask 21, a via holes having anarrowed opening area is not formed as described with reference to FIGS.2A to 2F.

Furthermore, when the first film 15 to be the first mask 25 is formedwith a material having light transmissibility, for example, a siliconoxide film used herein, and the second film 16 to be the second mask isformed with a material having light transmissibility, for example, asilicon nitride film used herein, the mask alignment, where the positionof the mask is aligned to the underlayer in an exposure step, can beconducted by an ordinary alignment method using light or an alignmentmethod using an image processing. It has been known that a silicon oxidefilm and a silicon nitride film transmit light in the wavelength regionof from 200 to 1,000 nm used for alignment.

Moreover, an etching stopper layer having a high dielectric constant(for example, a silicon nitride film, a silicon oxide film or a siliconoxide nitride film), which has been conveniently used, is not necessaryby utilizing the difference in characteristics of the materials. Forexample, when the conditions for etching the second film having a lowdielectric constant 14 (a xerogel film or a fluorine resin film) areselected in such a manner that the first film having a low dielectricconstant 13 (an organic film) is not etched, the wiring grooves 27 canbe formed in the second film having a low dielectric constant 14 to be awiring layer with good controllability. When the etching for forming thevia holes 26 is conducted, the second film having a low dielectricconstant 14 comprising a xerogel or a fluorine resin is etched, andsimultaneously the first film having a low dielectric constant 13comprising an organic film is etched.

A second embodiment of the process for producing a semiconductor deviceaccording to the invention will be described below with reference to theprocess diagram shown in FIGS. 5A to 5C. In FIGS. 5A to 5C, the samesymbols are attached to the same constitutional components as in FIGS.3A to 3F, 4G and 4H.

As shown in FIG. 5A, an underlying substrate 11 comprises, for example,a substrate 51 having thereon transistors (not shown in the figure), andan inter metal dielectric 52 covering thereon, in which wiring 53 isformed. A first film having a low dielectric constant 13 to be a lowerlayer of an inter level dielectric 12 on the underlying substrate 11 isformed, for example, with an inorganic film having a thickness of from300 to 800 nm.

A second film having a low dielectric constant 14 to be an upper layerof the inter level dielectric 12 is formed to a thickness, for example,of 400 nm on the first film having a low dielectric constant 13. Thesecond film having a low dielectric constant 14 is formed with afluorine resin. As the fluorine resin, the materials described for thefirst embodiment can be employed.

The inter level dielectric 12 comprising the first film having a lowdielectric constant 13 and the second film having a low dielectricconstant 14 is thus formed on the underlying substrate 11.

A first film 15 for forming a first mask as an inorganic mask is formedwith a silicon oxide film having a thickness of from 50 to 300 nm on theinter level dielectric 12, i.e., on the second film having a lowdielectric constant 14. A second film 16 for forming a second mask isformed with a silicon nitride film having a thickness of from 50 to 150nm. The film forming method of these films is the same as thosedescribed for the first embodiment.

According to the same manner as described with reference to FIG. 3C,only the second film 16 is etched to form openings 19 for forming wiringgrooves, so as to form a second mask 21 to be an etching mask forforming the wiring grooves in the inter level dielectric 12.

A resist film 22 is formed on the second film 16 and the first film 15by an ordinary resist coating technique (for example, a spin coatingmethod). Thereafter, the resist film 22 is patterned by a lithographytechnique to form openings 23 for forming via holes at positions withinthe openings 19 for forming the wiring grooves from the plan view of thesecond film 16.

Subsequently, only the first film 15 is etched by using the resist film22 as an etching mask to form openings 24 for forming via holes in theinter level dielectric 12, so as to form a first mask 25 to be anetching mask for forming the via holes in the inter level dielectric 12.

The second film having a low dielectric constant 14 of the inter leveldielectric 12 is etched by using an ordinary etching apparatus using thefirst mask 25 as an etching mask. As the etching conditions, forexample, nitrogen (N₂) (48 cm³/min) and helium (He) (200 cm³/min) areused as an etching gas, a microwave power is set at 1.35 kW (2.45 GHz),an RF plasma is set at 150 W, and a substrate temperature is set at −50°C. Because the resist film 22 is etched and completely removed in thisetching step, removal of the resist is not necessarily conducted.Furthermore, because the first film having a low dielectric constant 13comprising an inorganic film is present as an underlayer of the secondfilm having a low dielectric constant 14, the etching is stopped at theupper surface of the first film having a low dielectric constant 13.

As shown in FIG. 5B, the first mask 25 is then etched by using thesecond mask 21 comprising a silicon nitride film (or a metallic compoundfilm). In this step, because the second film having a low dielectricconstant 14 is formed with an organic film, the first film having a lowdielectric constant 13 comprising an inorganic film is etched with thesecond film having a low dielectric constant 14 as an etching mask, soas to form via holes 26. In this etching step, octafluorobutane (C₄F₈)and carbon monoxide (CO), for example, are used as an etching gas.

As shown in FIG. 5C, the second film having a low dielectric constant 14is etched by using the second mask 21 as an etching mask to form wiringgrooves 27. The etching conditions in this step are the same as theconditions for etching the second film having a low dielectric constant14. In this etching step, since the first film having a low dielectricconstant 13 comprises an inorganic film, the etching is stopped at theupper surface of the first film having a low dielectric constant 13.

While not shown in the figure, wiring is formed in the wiring grooves 27via a barrier metal layer, and plugs are formed in the via holes 26 viathe barrier metal layer, in the same manner as described with referenceto FIGS. 4G and 4H for the first embodiment.

In the second embodiment, as similar to the first embodiment, theprocess comprising from the step of forming the inter level dielectric12 to the step of forming the wiring and the plugs may be repeated toform a multi-layer wiring. The inter metal dielectric 52 among thewiring 53 may be formed with an organic film, such as a xerogel film ora fluorine resin film, by the similar process as the foregoing.

In the descriptions in the foregoing, while an example is described, inwhich the inter level dielectric 12 is formed on the underlayersubstrate 11 having semiconductor elements formed therein, theproduction process can be applied to the case where the inter leveldielectric 12, the via holes 26, the wiring grooves 27, the wiring 33and the plugs 34 having the constitution described above are formed on asubstrate having no semiconductor element.

According to the second embodiment of the process for producing asemiconductor device of the invention, the same function and effect asthe first embodiment of the process for producing a semiconductor devicecan be obtained.

A third embodiment of the process for producing a semiconductor deviceaccording to the invention will be described below with reference to theprocess diagram shown in FIGS. 6A to 6F. In FIGS. 6A to 6F, the samesymbols are attached to the same constitutional components as in FIGS.3A to 3F.

As shown in FIG. 6A, an underlying substrater 11 comprises, for example,a substrate 51 having thereon transistors (not shown in the figure), andan inter metal dielectric 52 covering thereon, in which wiring 53 isformed. A first film having a low dielectric constant 13 to be a lowerlayer of an inter level dielectric 12 is formed to a thickness of, forexample, from 300 to 800 nm on the underlying substrate 11. The firstfilm having a low dielectric constant 13 becomes an inter leveldielectric (ILD) between wiring layers, and can be formed with anorganic film having a specific inductive capacity of about 2.5. Forexample, it can be formed with the same material as described for thefirst embodiment in the same film forming method as described therefor.

An intermediate film 41 to be an etching mask is formed with, forexample, a silicon oxide film on the first film having a low dielectricconstant 13. The method for forming the same may be the same formingmethod of the silicon oxide film as described for the first embodiment.

A second film having a low dielectric constant 14 to be an upper layerof the inter level dielectric 12 is formed to a thickness, for exampleof 400 nm on the intermediate film 41. The second film having a lowdielectric constant 14 is formed with a fluorine resin. Examples of thefilm include a fluorocarbon film, such as a cyclic fluorine resin,polytetrafluoroethylene (PTFE), amorphous PTFE (for example, Teflon AF,a trade name, produced by Du Pont Corp.), fluorinated aryl ether andfluorinated polyimide. Alternatively, a xerogel (for example, poroussilica) may be employed. The method for forming the fluorine resin filmmay be the same forming method as described for the first embodiment.Alternatively, the second film having a low dielectric constant 14 isformed with a xerogel film. The method for forming the xerogel film maybe the same forming method as described for the first embodiment.

According to the manner described in the foregoing, the inter leveldielectric 12 comprising the first film having a low dielectric constant13, the intermediate film 41 and the second film having a low dielectricconstant 14 is formed on the underlying substrate 11.

As shown in FIG. 6B, a first film 15 for forming a first mask as aninorganic mask is formed with a silicon oxide film having a thickness offrom 50 to 300 nm on the inter level dielectric 12, i.e., on the secondfilm having a low dielectric constant 14. A second film 16 for forming asecond mask is formed with a silicon nitride film having a thickness offrom 50 to 150 nm. The film forming method of these films may be thesame forming method as described for the first embodiment.

Before forming the silicon oxide film, it is preferred that a filmhaving a larger silicon content than the silicon nitride film, theamorphous silicon, the silicon nitride oxide film or the stoichiometricamount is formed, depending on necessity, particularly in the case wherethe oxidation of the second film having a low dielectric constant 15causes a problem. That is, a CVD film is formed under a reductiveatmosphere. The film thickness is preferably as thin as possible, and isgenerally about 10 nm. As described herein, the first film 15 is formedwith a silicon oxide film that is excellent in light transmissibility ina wavelength range (for example, from 200 to 1,000 nm) used foralignment, and the second film 16 is also formed with a silicon nitridefilm having light transmissibility in a wavelength range (for example,from 200 to 1,000 nm) used for alignment.

As shown in FIG. 6C, a resist film 17 is formed on the second film 16 byan ordinary resist coating technique (for example, a spin coatingmethod). Thereafter, the resist film 17 is patterned by a lithographytechnique to form openings 18 for forming wiring grooves.

Subsequently, the second film 16 is etched by using the resist film 17as an etching mask to form openings 19 for forming wiring grooves, so asto form a second mask 21 to be an etching mask for forming wiringgrooves in the inter level dielectric 12. The etching step may beconducted in the same manner as for the first embodiment. Thereafter,the resist film 17 is removed by ashing. FIG. 6C shows the state beforeremoving the resist film 17.

As shown in FIG. 6D, a resist film 22 is formed on the second film 16and the first film 15 by an ordinary resist coating technique (forexample, a spin coating method). Thereafter, the resist film 22 ispatterned by a lithography technique to form openings 23 for forming viaholes at positions within the openings 19 for forming the wiring groovesfrom the plan view of the second film 16. Even when deviation occurs onaligning the masks, it is necessary that at least a part of the opening23 overlaps the opening 19.

Subsequently, only the first film 15 is etched by using the resist film22 as an etching mask to form openings 24 for forming via holes in theinter level dielectric 12, so as to form a first mask 25 to be anetching mask for forming the via holes in the inter level dielectric 12.

The second film having a low dielectric constant 14 of the inter leveldielectric 12 is etched by using an ordinary etching apparatus using thefirst mask 25 as an etching mask. As the etching conditions, forexample, nitrogen is used as an etching gas, and ammonia and a hydrogengas may also be used depending on necessity. In this etching step, afluorine carbide series gas and carbon monoxide are not necessary.Because the intermediate film 41 comprising a silicon oxide film ispresent as an underlayer of the second film having a low dielectricconstant 14, the etching is stopped at the intermediate film 41. In theetching step, the resist film 22 is etched and completely removed whenthe second film having a low dielectric constant 14 comprising anorganic film is etched. Therefore, there is no necessity to conductresist ashing in this stage.

As shown in FIG. 6E, the first mask 25 and the intermediate film 41 areetched by using an ordinary etching apparatus using the second mask 21and the second film having a low dielectric constant 14 as an etchingmask. That is, the first mask 25 is etched as transferring the openings19 formed in the second mask 21 for forming the wiring grooves, andopenings 42 for forming via holes in the intermediate film 41 are formedby etching. As the etching conditions, for example, octafluorobutane(C₄F₈) (5 cm³/min), carbon monoxide (5 cm³/min) and argon (20 cm³/min)are used as an etching gas, and an RF plasma is set at 600 W.

As shown in FIG. 6F, by using the first mask 25 (the second mask 21) andthe intermediate film 41 as an etching mask, the second film having alow dielectric constant 14 and the first film having a low dielectricconstant 13 are etched, to form wiring grooves 27 in the second filmhaving a low dielectric constant 14, and simultaneously to form viaholes 26 in the first film having a low dielectric constant 13. As theetching gas in this etching step, nitrogen (N₂) is used, and ammonia anda hydrogen gas may also be used depending on necessity.

While not shown in the figure, wiring comprising metal is formed in thewiring grooves 27 via a barrier signal metal layer, and plugs comprisingmetal are formed in the via holes 26 via the barrier metal layer, in thesame manner as described with reference to FIGS. 4G and 4H.

According to the third embodiment described with reference to FIGS. 6Ato 6F, the same function and effect as the first embodiment describedwith reference to FIGS. 3A to 3F can be obtained.

The intermediate film 41 may also be formed with a silicon nitride oxidefilm or a silicon nitride film. Alternatively, it may be formed with anorganic film that becomes an etching mask with respect to the first filmhaving a low dielectric constant 13 and becomes an etching stopper withrespect to the second film having a low dielectric constant 14.

The xerogel film, the fluorine resin film and the other organic filmsare being employed in the wiring structure for the object of suppressingthe wiring capacitance increasing with the scale down. In this case, theorganic film may be employed as a material having a specific inductivecapacitance of 3 or less, the fluorine resin may be employed as anorganic film material having a specific inductive capacitance of 2.5 orless, and the xerogel film, which is a gel having a network structurecontaining no water, may be employed as a material having a specificinductive capacitance of 2.5 or less.

Among the xerogels described in the foregoing, a film that can be usedin a semiconductor device includes a silica series gel. For example,Nanoporous Silica produced by Nanoglass LLC can be used. However, thexerogel film of this type is inferior in mechanical strength, heatconductivity, heat resistance, water resistance and adhesiveness incomparison to the conventional inter level dielectric. In particular,the heat conductivity is remarkably poor as is from 1/10 to 1/100 of theorganic film.

On the other hand, as the fluorine resin, commercial products, such as afilm formed by plasma CVD (reported by NEC Corp. in IEDM (InternationalElectron Devices Meeting) on 1997), Teflon (produced by Du Pont Corp.)and fluorinated polyimide (produced by Du Pont Corp.) have beendeveloped. As those under development, there are a vapor deposition filmof fluorinated Parylene and a copolymer of a fluorine resin and silica.However, these films are inferior in mechanical strength, heatconductivity, heat resistance and adhesiveness in comparison to theorganic polymer having a specific inductive capacity of 2.5 or more.

Under the circumstances, the invention employs a combination of axerogel film and an organic film having a better film property than thexerogel film, or a combination of a fluorine resin film and an organicfilm having a better film property than the fluorine resin film, asdescribed in the embodiments above, so as to realize to form a highlyreliable wiring structure.

That is, the xerogel film or the fluorine resin film is used only in thepart between the wirings, at which the wiring capacitance is increasedby the scale down, and the other parts are formed with the organic filmor the inorganic film having a low dielectric constant. Specifically, ina semiconductor device having the minimum interval of wiring, inparticular, one of a design rule of 0.18 μm or less, the xerogel film orthe fluorine resin film is applied to the part where the wiring intervalis 0.3 μm or less because the wiring capacity is remarkably increased atthe part where the wiring interval is 0.3 μm or less. According to this,an effect of decreasing the wiring capacitance can be obtained. On theother hand, there is no large influence at the part where the wiringinterval is larger than 0.3 μm (for example, one between wiring layersvertically stacked). Therefore, it is sufficient to use an organic filmhaving a specific inductive capacity of 3 or less at the part where thewiring interval exceeds 0.3 μm.

A fourth embodiment of the process for producing a semiconductor deviceaccording to the invention will be described below with reference to theprocess diagram shown in FIGS. 7A to 7I.

As shown in FIG. 7A, a substrate 60 is constituted, for example, byforming a semiconductor element, such as a transistor, on asemiconductor substrate, and then forming wiring and dielectrics. Apassivation film 61 is formed with a material, by which the wiringmaterial is not diffused, such as a silicon nitride film, having athickness of about 50 nm on the uppermost layer of the substrate 60.

Thereafter, a first inter level dielectric 62, in which a via hole isformed, is formed with a silicon oxide series material, such as asilicon oxide (SiO₂) film (an inorganic film) having a thickness of 500nm, and then a second inter level dielectric 63, in which wiring isformed, is formed with an organic material, such as a polyaryl etherfilm having a thickness of 500 nm. Subsequently, a first film 64 forforming a first mask is formed with a silicon oxide film having athickness of 100 nm, and then a second film 65 for forming a second maskis formed with a silicon nitride film having a thickness of 100 nm.

As shown in FIG. 7B, a resist mask 81 for forming a wiring groove isformed on the second film 65 by conducting an ordinary resist coatingprocess and an ordinary lithography process. In the resist mask 81, anopening 82 for forming the wiring groove is formed.

Subsequently, as shown in FIG. 7C, the first film 65 is etched by usingthe resist mask 81 (see FIG. 7B) to open a wiring groove pattern 66 forforming the wiring groove, so as to form a second mask 67. In thisetching step, an ordinary parallel flat palate type plasma etchingapparatus is used, and trifluoromethane (CHF₃), argon (Ar) and oxygen(O₂) are used as an etching gas. The substrate temperature is 0° C.Thereafter, the resist mask 81 (see FIG. 7B) is removed.

As shown in FIG. 7D, a resist mask 83 used for forming a via hole isformed on the second mask 67 and the wiring groove pattern 66 by againconducting an ordinary resist coating process and an ordinarylithography process. In the resist mask 83, an opening 84 for formingthe via hole is formed in such a manner that it at least overlaps thewiring groove pattern 66.

As shown in FIG. 7E, the first film 64 is etched by using the resistmask 83 as an etching mask to form a via hole pattern 68 for forming thevia hole, so as to form a first mask 69. In etching of the first film64, an ordinary parallel flat palate type plasma etching apparatus isused, and octafluorobutane (C₄F₈), argon (Ar) and oxygen (O₂) are usedas an etching gas. The substrate temperature is 0° C.

As shown in FIG. 7F, the second inter level dielectric 63 is etched byusing the first mask 69 as an etching mask to extend the via holepattern 68. In this etching step, the resist mask 83 is simultaneouslyetched and removed. In the etching step of the second inter leveldielectric 63, an ordinary high-density plasma etching apparatus, andammonia (NH₃) is used as an etching gas. The substrate temperature is−20° C.

Subsequently, as shown in FIG. 7G, the wiring groove pattern 66 isextended to the first mask 69 by using the second mask 67 as an etchingmask. At the same time, the first inter level dielectric 62 is etched byusing the second inter level dielectric 63 as an etching mask to form avia hole 70. In this etching step, an ordinary parallel flat palate typeplasma etching apparatus is used, and octafluorobutane (C₄F₈), argon(Ar) and oxygen (O₂) are used as an etching gas. The substratetemperature is set at 0° C.

As shown in FIG. 7H, the second inter level dielectric 63 is etched byusing the first mask 69 as an etching mask to form a wiring groove 71.In the etching step, an ordinary high-density plasma etching apparatus,and ammonia (NH₃) is used as an etching gas. The substrate temperatureis −100° C.

Thereafter, as shown in FIG. 7I, the passivation film 61 exposed at thebottom of the via hole 70 is etched. At this time, the second mask 67(see FIG. 7H) comprising the same material as the passivation film isalso etched and removed. In this etching step, in order to selectivelyconduct anisotropic etching of the silicon nitride film, an ordinaryhigh-density plasma etching apparatus is used, and sulfur hexafluoride(SF₆) is used as an etching gas. The substrate temperature is 0° C. As aresult, the wiring groove 71 is formed in the second inter leveldielectric 63, and the via hole 70 is formed in the first inter leveldielectric 62 and the passivation film 61 as being connected to thebottom of the wiring groove 71.

While a silicon oxide (SiO₂) film is used as the first inter leveldielectric 62 in this embodiment, silicon oxide fluoride (SiOF), forexample, may also be used.

While the second mask layer 65 is formed with a silicon nitride film, itmay be formed with a high melting point metal film or a high meltingpoint metal compound film, such as a titanium nitride film. That is, anymaterial may be used as far as the material has etching selectivity tothe silicon oxide series material. It is preferred to use a film havinglight transmissibility, by which optical alignment can be conducted.

In the fourth embodiment described with reference to FIGS. 7A to 7I,while an example is described, in which the first and second inter leveldielectrics 62 and 63 are formed on the substrate 60 havingsemiconductor elements formed therein, the production process describedwith reference to 7A to 7I can be applied to the case where the firstand second inter level dielectrics 62 and 63, the via hole 70 and thewiring groove 71 are formed on a substrate having no semiconductorelement.

The fourth embodiment of the process for producing a semiconductordevice comprises a step of forming, on the second inter level dielectric63, the first mask 69 to be an etching mask for etching the first andsecond inter level dielectrics 62 and 63, and a step of forming, on thefirst mask 69, the second mask 67, which comprises a material differentfrom the first mask 69, to be an etching mask for etching the secondinter level dielectric 63. Therefore, it is possible that the first andsecond inter level dielectrics 62 and 63 are etched by using the firstmask 69 as an etching mask to form the via hole 70, and then the secondinter level dielectric 63 is etched by using the second mask 67 havingthe wiring groove pattern 66, which is different from the first mask 69,as an etching mask to form the wiring groove 71.

Because the second inter level dielectric 63, which becomes an interlevel dielectric between wiring in the same wiring layer, is formed witha polyaryl ether film, which is an organic polymer film, the dielectricconstant between the wirings is decreased in comparison to the casewhere the second inter level dielectric 63 is formed with a siliconoxide series material, and thus the wiring capacitance is also decreasedin comparison to the case where the second inter level dielectric 63 isformed with a silicon oxide series material.

Furthermore, the resist process (a step of patterning a resist film)used for forming the first and second masks 69 and 67 can be conductedunder the condition in that the second inter level dielectric 63 is notexposed. That is, the first film 64 is formed as an underlayer layer inthe resist process for forming the second mask 67, and the first film 64covers the second inter level dielectric 63 in the resist process forforming the first mask 69. Therefore, the restoration treatment of theresist can be conducted without exposing the second inter leveldielectric 63, i.e., an organic film, in which the resist films 81 and83 formed in the resist processes can be removed, and the resist films81 and 83 are again formed and patterned. Furthermore, because theresist film 83 to be an etching mask for forming the first mask 69 canbe removed simultaneously with the etching of the second inter leveldielectric 63, the operation of removing the resist film 83 is notnecessary. Therefore, the process can be simplified.

In the resist process for forming the via hole pattern 68 for formingthe via hole 70 in the first film 64, i.e., in the step of forming theopening 84 in the resist film 83, even when misalignment occurs to formthe opening 84 in the resist film 83 deviating from the wiring groovepattern 66 formed in second mask 67, a via hole pattern (not shown inthe figure) to be a pattern for forming the via hole also in the secondmask 67 can be formed. The detail of this process will be describedbelow with reference to FIGS. 8A to 8F. In each of FIGS. 8A to 8F, aplan view for the arrangement is shown in the upper part, and a crosssectional view is shown in the lower part.

As shown in FIG. 8A, an opening 84 formed in a resist film 83 forforming a via hole pattern is formed deviating from a wiring groovepattern 66 formed in a second mask 67. Even in such a case, by using theresist film 83 as an etching mask, the second mask 67 is etched, andfurther a first film 64 is etched, to form a via hole pattern 68, so asto form a first mask 69, as shown in FIG. 8B. By this step, the wiringgroove pattern 66 and the via hole pattern 68 are formed in the secondmask 67.

As shown in FIG. 8C, the second inter level dielectric 63 is then etchedby using the first mask 69 as an etching mask to form the via holepattern 68. Therefore, the via hole pattern 68 having the opening areathat conforms to its design can be formed. In this etching step, theresist mask 83 (see FIG. 8B) is simultaneously etched and removed.

Subsequently, as shown in FIG. 8D, the wiring groove pattern 66 isextended to the first mask 69 by using the second mask 67 as an etchingmask. At the same time, the first inter level dielectric 62 is etched byusing the second inter level dielectric 63 as an etching mask to form avia hole 70. As a result, because the via hole pattern 68 formed in thesecond inter level dielectric 63 is formed to have the opening area thatconforms to its design, the via hole 70 is formed to have the openingarea that conforms to its design.

As shown in FIG. 8E, the second inter level dielectric 63 is then etchedby using the first mask 69 as an etching mask to form a wiring groove71. Thereafter, as shown in FIG. 8F, the passivation film 61 exposed atthe bottom of the via hole 70 is etched. At this time, the second mask67 (see FIG. 8E) comprising the same material as the passivation film isalso etched and removed. As a result, the wiring groove 71 is formed inthe second inter level dielectric 63, and the via hole 70 is formed inthe first inter level dielectric 62 and the passivation film 61 as beingconnected to the bottom of the wiring groove 71. As described in theforegoing, the via hole pattern 68 having an opening area that conformsto its design is formed in the second inter level dielectric 63, and thevia hole 70 is not filled with the inter level dielectric after formingthe via hole 70. Therefore, the via hole 70 having a narrowed openingarea as in the case of FIGS. 2A to 2F is not formed.

In the embodiment described herein, the opening area of the via hole canbe ensured even when the via hole pattern deviates from the wiringgroove pattern due to misalignment occurring on forming the via holepattern. However, according to the process for producing a semiconductordevice of the invention, the effect of ensuring the opening area of thevia hole can be obtained in any case where the wiring groove pattern andthe via hole pattern relatively deviate from each other.

Furthermore, the first film 65 to be the first mask 69 is formed with amaterial having light transmissibility, such as a silicon oxide filmused herein, and the second film 65 to be the second mask is formed witha material having light transmissibility, such as a silicon nitride filmused herein. Therefore, in the exposure step hereafter, the maskalignment to align the position of the mask to the underlayer can beconducted by alignment using light or alignment using an imageprocessing. It has been known that a silicon oxide film and a siliconnitride film transmit light in the wavelength region of from 200 to1,000 nm used for alignment.

Moreover, an etching stopper layer having a high dielectric constant(for example, a silicon nitride film, a silicon oxide film or a siliconoxide nitride film), which has been conventionally used, is notnecessary by utilizing the difference in characteristics of thematerials between the first inter level dielectric 62 and the secondinter level dielectric 63. For example, when the condition in that thesecond inter level dielectric 63 (an organic film) is etched but thefirst inter level dielectric 62 is not etched is selected, the wiringgrooves 71 can be formed in the second inter level dielectric 63 to be awiring layer with good controllability. When the etching for forming thevia holes 70 is conducted, the wiring groove pattern 66 is extended tothe first mask 69 comprising a silicon oxide film, and at the same time,the first inter level dielectric 62 comprising a silicon oxide film isetched as described in the foregoing.

According to the invention described in the foregoing, the processcomprises the step of forming, on the inter level dielectric, the firstmask to be an etching mask for etching the inter level dielectric, and astep of forming, on the first mask, the second mask to be an etchingmask for etching the inter level dielectric, the second mask comprisinga material different from the first mask. Therefore, the inter leveldielectric is etched by using the first mask as an etching mask to formthe via holes, and then the inter level dielectric is etched by usingthe second mask as an etching mask to a pattern different from the firstmask, to form the wiring grooves.

Furthermore, according to the production process, in which the upperlayer of the inter metal dielectric between the wirings in the samewiring layer is formed with a xerogel film or a fluorine resin film, thewiring capacitance can be reduced. When an organic film or an inorganicfilm is used only in the inter level dielectric between the wiringslayer among the inter level dielectrics, deterioration of the mechanicalstrength of the whole inter level dielectrics can be suppressed evenwhen the inter level dielectric between the wirings is formed with axerogel or a fluorine resin. Therefore, a semiconductor device combiningcopper wiring, a fluorine resin and an organic film, or a semiconductordevice combining copper wiring, a xerogel and an organic film can beformed without deterioration of the yield.

In the resist process for forming the second mask, the first film isformed on the underlayer, and in the resist process for forming thefirst mask, the first film covers the inter level dielectric. Therefore,the resist processes for forming the first and second masks can beconducted under the condition in that the inter level dielectric is notexposed, and thus the restoration treatment of the resist film can beconducted in the resist process.

Even when misalignment occurs on forming the first mask having a patternfor forming the via hole, the pattern for forming the via hole can alsobe formed in the second mask. Therefore, the narrowing of the openingarea of the via hole described in FIGS. 2A to 2F does not occur.

By forming the first mask and the second mask with a material havinglight transmissibility, the mask alignment in the exposure step of thelithography process conducted after forming the film for forming thefirst mask and the film for forming the second mask can be conducted inthe same alignment method as the conventional process.

1. A process for producing a semiconductor device comprising an interlevel dielectric comprising a xerogel film or an organic film, saidprocess comprising a step of forming on said inter level dielectric, afirst light transmissible mask to be an etching mask for etching saidinter level dielectric; a step of forming, on said first mask, a secondlight transmissible mask comprising a different material from said firstmask to be an etching mask for etching said inter level dielectric, saidsecond light transmissible mask being formed with a silicon nitride; astep of forming, on said second light transmissible mask, a first resistfilm that is used as a mask for etching said second light transmissiblefilm; removing said first resist film; a step of forming, on said firstand second light transmissible masks, a second resist film for etchingsaid first light transmissible mask, and first and second levels of saidinter level dielectric; and removing said second resist film.
 2. Aprocess for producing a semiconductor device as claimed in claim 1,wherein a pattern for forming a wiring groove is formed in said secondmask, and a pattern for forming a via hole is formed in said first maskin such a manner that said pattern for forming a via hole at leastoverlaps said pattern for forming a wiring groove.
 3. A process forproducing a semiconductor device as claimed in claim 2, wherein a methodfor forming a pattern for forming a wiring groove in said second mask,and forming a pattern for forming a via hole in said first mask in sucha manner that said pattern for forming a via hole at least overlaps saidpattern for forming a wiring groove comprises a step of forming a firstfilm for forming said first mask on said inter level dielectric, andthen forming a second film for forming said second mask on said firstfilm; a step of forming said pattern for forming a wiring groove in saidsecond film to form said second mask; and a step of forming said patternfor forming a via hole in said first film in such a manner that saidpattern for forming a via hole at least overlaps said pattern forforming a wiring groove, to form said first mask.
 4. A process forproducing a semiconductor device as claimed in claim 1, wherein a lowerlayer of said inter level dielectric between wiring layers is formedwith an organic film, and an upper layer of said inter level dielectricbetween wiring of the same wiring layer is formed with a xerogel film oran organic film.
 5. A process for producing a semiconductor device asclaimed in claim 4, wherein a pattern for forming a wiring groove isformed in said second mask, and a pattern for forming a via hole isformed in said first mask in such a manner that said pattern for forminga via hole at least overlaps said pattern for forming a wiring groove.6. A process for producing a semiconductor device as claimed in claim 5,wherein a method for forming a pattern for forming a wiring groove insaid second mask, and forming a pattern for forming a via hole in saidfirst mask in such a manner that said pattern for forming a via hole atleast overlaps said pattern for forming a wiring groove comprises a stepof forming a first film for forming said first mask on said inter leveldielectric, and then forming a second film for forming said second maskon said first film; a step of forming said pattern for forming a wiringgroove in said second film to form said second mask; and a step offorming said pattern for forming a via hole in said first film in such amanner that said pattern for forming a via hole at least overlaps saidpattern for forming a wiring groove, to form said first mask.
 7. Aprocess for producing a semiconductor device as claimed in claim 6,wherein said process comprises after forming said first mask, a step ofcontinuously etching said inter level dielectric by using a resist filmused as an etching mask for forming said first mask and said first maskas an etching mask, to form a via hole; and a step of forming a wiringgroove in said first mask and said upper layer of said inter leveldielectric by etching using said second mask.
 8. A process for producinga semiconductor device as claimed in claim 1, wherein a lower layer ofsaid inter level dielectric between wiring layers is formed with aninorganic film, and an upper layer of said inter level dielectricbetween wiring of the same wiring layer is formed with an organic film.9. A process for producing a semiconductor device as claimed in claim 8,wherein a pattern for forming a wiring groove is formed in said secondmask, and a pattern for forming a via hole is formed in said first maskin such a manner that said pattern for forming a via hole at leastoverlaps said pattern for forming a wiring groove.
 10. A process forproducing a semiconductor device as claimed in claim 9, wherein a methodfor forming a pattern for forming a wiring groove in said second mask,and forming a pattern for forming a via hole in said first mask in sucha manner that said pattern for forming a via hole at least overlaps saidpattern for forming a wiring groove comprises step of forming a firstfilm for forming said first mask on said inter level dielectric, andthen forming a second film for forming said second mask on said firstfilm; a step of forming said pattern for forming a wiring groove in saidsecond film to form said second mask; and a step of forming said patternfor forming a via hole in said first film in such a manner that saidpattern for forming a via hole at least overlaps said pattern forforming a wiring groove, to form said first mask.
 11. A process forproducing a semiconductor device as claimed in claim 10, wherein saidprocess comprises after forming said first mask, a step of forming anopening for forming a via hole in said upper layer of said inter leveldielectric by using said first mask as an etching mask; a step offorming an opening for forming a wiring groove in said first mask byetching using said second mask, and forming said via hole in said lowerlayer of said inter level dielectric by using said upper layer of saidinter level dielectric as a mask; and a step of forming said wiringgroove in said upper layer of said inter level dielectric by using saidsecond mask as an etching mask.